Field of the Invention
The disclosure generally relates to ESD (ElectroStatic Discharge) protection circuits, and more specifically, to ESD protection circuits with low parasitic capacitances and high trigger voltages.
Description of the Related Art
In order to avoid ESD events to generate large currents and make circuit systems damaging, ESD protection circuits are widely used in a variety of integrated circuits (ICs). Specifically, high-power RF (Radio Frequency) power amplifiers require ESD protection circuits having low parasitic capacitances and high trigger voltages. However, most ESD protection circuits with sufficient ESD immunity have relatively large parasitic capacitances, which increase capacitive loading and worsen high-frequency frequency response of circuit systems. For example, the transfer function pole of a circuit moves toward a lower frequency, and therefore the operation bandwidth of the circuit becomes narrower. Thus, to design new ESD protection circuits is needed to solve the problems of large parasitic capacitance and low trigger voltage of traditional ESD protection circuit designs.